Figures
This repository contains an informal library of figures created in various ways and for various purposes which may be of use to others. These figures are typically described in TikZ, Inkscape or generated by Python (usually by outputting machine generated SVG or TikZ source).
Though the figures are intended to be aesthetically pleasing, their descriptions are often not. Please be aware of this if you are considering adapting a figure!
You can clone the repository containing these figures over on GitHub.

Tickysim SpiNNaker Node Architecture
An illustration of the architecture of a node in the Tickysim SpiNNaker model. Implementation is a "just a little" messy...
SpiNN-Link Pipeline
A very hand-wavy version of the pipeline taken by packets using the high-speed serial links in SpiNNaker SpiNNaker.
SpiNNaker Three-Board
A diagram showing how a three-board configuration can be used to form a toroid from three SpiNNaker boards.
High-Level SpiNNaker Chip Architecture
An illustration of what the SpiNNaker chip kind-of-sort-of looks like from an extremely high-level and network-centric point of view.
Arrangement of chips on a SpiNNaker board
Shows the logical arrangement of chips on a SpiNNaker board and the collections of connections assigned to each SpiNN-link connection.
SpiNNaker Arbiter Tree
Shows the arbiter tree in SpiNNaker.
Neurogrid Output Arbitration
Neurogrid chip topology showing the mechanism used to arbitrate the chip's shared output port.
BrainScaleS Wafer
An illustration of what the BrainScaleS wafer kind-of-sort-of looks like.